High quality ultra-thin oxide films are critical components in the smallest transistors, such as the 14 nm technology. The ultra-thin oxide layers are deposited in the form of gate stacks and are used as gate oxides. The ultra-thin oxide layers are formed by atomic layer deposition (ALD) processes. ALD processes expose a substrate surface to a series of sequential non-overlapping precursor pulses. ALD is capable of producing ultra-thin films with control over thickness and composition at the atomic level.
The current technology for ALD gate oxide deposition on Si, Ge and SiGe substrates involves temperatures of 250° C. to 300° C. for Al2O3 and HfO2 deposition. Higher temperature is considered necessary by artisans for the fast reaction of the metal precursors (i.e., TMA and TEMAH) with water and efficient removal of unreacted residual precursors from the chamber. The present inventors have identified two main disadvantages for high temperature ALD: 1) At temperatures as high as 250 or 300° C., a thin layer of SiO2 or GeSiOx on SiGe (or GeOx on Ge or GaInOx on InGaAs) can form on the sample surface instantly after insertion into the chamber. Such SiO2, SiGeOx, GeOx, or InGaOx layer can act as a nucleation barrier for the oxide or generate interface states near or at the oxide/semiconductor interface or increase the effective oxide thickness. See, e.g., M.-H. Cho, et al, “Interfacial characteristics of HfO2 films grown on strained Si0.7Ge0.3 by atomic layer deposition,” Appl. Phys. Lett. 84, 1171 (1984). 2) In the case of Ge and SiGe, the high temperatures create a high probability of Ge out—diffusion from the semiconductor side into the oxide. The Ge diffusion into the oxide creates higher gate leakage, as the Ge out-diffusion is expected to change the electronic structure of the substrate and degrade the gate oxide. Channel performance is decreased due to loss of Ge in the channel. Other known problems caused by such diffusion include earlier oxide break down, and higher interface trap densities at the oxide/SiGe interface. See, e.g., Lu et al., “Ge diffusion in Ge metal oxide semiconductor with chemical vapor deposition HfO2 dielectric,” Appl. Phys. Lett 87, 051922.
SiGe also has application as a substrate material (or strain-relaxed buffer) for strained n-Si in order to improve electron mobility in the Si channel of a MOSFET. Currie et al., “Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates,” J. Vac. Sci. Technol. B 19, (2001).
p-SiGe provides high hole mobility and therefore has potential to serve as the channel material in p-MOSFETs. See, Gomez at al. “Enhanced Hole Mobility in High Ge Content Asymmetrically Strained-SiGe p-MOSFETs,” IEEE Elec. Dev. Lett, 31 (8) (2010) p 782. SiGe provide much higher hole mobility than silicon and SiGe provides better electron mobility than Si, making the material suitable for both p-MOSFET and n-MOSFET. SiGe MOSFET scaling requires a low-leakage, high-k oxide with a relatively defect-free interface with SiGe.
There are very few reports on deposition of gate oxides on SiGe and oxide/SiGe interface characterization. Von Hartmaan et al. reported the deposition of a tri-layer of Al2O3/HfO2/Al2O3 on a Si0.7Ge0.3 p-MOSFET channel via ALD at 300° C. The overall oxide quality and HfO2 trap density was characterized by measuring the Id-Vd and p-MOSFET's low frequency drain noise. See, Von Haartman et al., Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics,” Solid-State Elec., 48(12), (2004) p 2271. The possibility of device integration in SiGe devices for this tri-layer was separately reported. Ostling et al. concluded that this tri-layer has better drain noise compared to pure Al2O3 and HfO2. See, Ostling et al., Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics,” Proc. 25th International Conference On Microelectronics (2006). However, the oxide and oxide/interface were not independently characterized by measuring C-V curves. In both reports, HR-TEM images showed presence of a thin SiOx layer at the Al2O3/SiGe interface.
Wu et al reported deposition of a 4 nm thick mixed layer of Al2O3/HfO2/Al2O3 on strained p-SiGe by dosing TMA, HfCl4 and water at 300° C., and observed a 0.7 nm thick layer of mixed Al2O3—SiOx when an HF clean was followed by a water rinse. Wu et al., “Structural and electrical characterization of Al2O3/HfO2/Al2O3 on strained SiGe,” Solid-State Elec., 49, (2005) p 193. In the Wu et al. and Von Haartman et al reports, the Al2O3 is employed as a spacer between HfO2 and SiGe to prevent interfacial reactions (i.e., Ge out-diffusion) during the routine post deposition annealing of the devices. Despite low gate leakage as a function of gate bias, the device C-V curves showed high fixed and interface trap charges as well as false inversion.
To control and reduce the density of interface trap states, Han et al applied electron cyclotron resonance (ECR) plasma post-nitridation after Al2O3 deposition at 250° C. by ALD on SiGe0.25. Han et al., “Reduction in Interface Trap Density of Al2O3/SiGe Gate Stack by Electron Cyclotron Resonance Plasma Post-nitridation,” Appl. Phys. Express 6, 051302 (2013). Ostling et al compared HfO2, Al2O3 and HfAlOx deposited on strained p-SiGe at 300° C. by ALD and concluded that HfAlOx has the best properties in terms of MOSFET drain noise and hole mobility. Oestling et al., Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics,” Proc. 25th International Conference On Microelectronics (2006). Si—Ge and Ge materials are used in 3D architectures, including the finFET, which utilize the SiGe(001) and (110) crystal faces simultaneously, thus requiring passivation methods for the (110) face in order to ensure a pristine 3D surface prior to further processing.
For III-V finFETs, again (001) and (110) crystal faces will also be employed and need to be passivated. An additional challenge for III-V semiconductor based FETs is the large density of trap states at the semiconductor/oxide interface. High-k materials such as HfO2 and Al2O3 provide better performance, but continued aggressive down scaling of the gate oxide requires maximizing the nucleation density of the high-k atomic layer deposition (ALD) precursors, so that the dielectric closes to form a continuous film on the substrate in a small number of ALD reaction cycles.
Compound semiconductor based MOS devices also suffer from a relatively high density of interface trap states (Dit) at the semiconductor/high-k interface. These electronic trap states result from physical defects at the interface such as dangling bonds, metallic bonds, strained bonds, and defective native oxides. These can result directly from poor initiation of high-k ALD on the semiconductor surface. To increase drive current and minimize power consumption of III-V devices, it is important to minimize the Dit. Subcutaneous oxidation of the substrate and plasma induced damage during pre-ALD in-situ surface cleans can also generate Dit. One of the present inventors and colleagues have previously demonstrated hydrogen to remove native oxide. W. Melitz, J. Shen, T. Kent, A. C. Kummel, and R. Droopad, “InGaAs surface preparation for atomic layer deposition by hydrogen cleaning and improvement with high temperature anneal,” J. App. Phys. 110, 013713 (2011). Others have shown that at high temperature (e.g. 300° C.) use of TMA and H2 plasma after a wet cleaning and prior to ALD of Al2O3 and HfO2 can improve capacitance voltage (C-V) characteristics with deposition at 300° C. Andrew D. Carter, William J. Mitchell, Brian J. Thibeault, Jeremy J. M. Law, and Mark J. W. Rodwell, “Al2O3 Growth on (100) In0.53Ga0.47As Initiated by Cyclic Trimethylaluminum and Hydrogen Plasma Exposures,” Applied physics express 4, 091102 (2011); V Chobpattana, J Son, J J M Law, R Engel-Herbert, C Y Huang, S Stemmer, “Nitrogen-passivated dielectric/InGaAs interfaces with sub-nm equivalent oxide thickness and low interface trap densities,” Applied Physics Letters 102 (2), 022907 (2013).